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integrated circuit systems, inc. general description features ICS9250-13 block diagram pentium is a trademark of intel corporation i 2 c is a trademark of philips corporation frequency generator & integrated buffers for pentium/pro tm 9250-13 rev a 3/25/99 pin configuration ? 3.3v outputs: sdram, pci, ref, 48/24mhz ? 2.5v or 3.3v outputs: cpu ? 20 ohm cpu clock output impedance ? 20 ohm pci clock output impedance ? skew from cpu (earlier) to pci clock - 1 to 4 ns, center 2.6 ns. ? no external load cap for c l =18pf crystals ? 250 ps cpu, pci clock skew ? 400ps (cycle to cycle) cpu jitter ? smooth frequency switch, with selections from 50 to 83.3 mhz cpu. ?i 2 c interface for programming ? 2ms power up clock stable time ? clock duty cycle 45-55%. ? 56 pin 300 mil ssop package ? 3.3v operation, 5v tolerant input. 56-pin ssop power groups vddref = ref (0:1), x1, x2 vddpci = pciclk_f, pciclk(0:5) vddsdr = sdram (0:11), supply for pll core, vdd48 = 24mhz, 48mhz vddlioapic = ioapic vddl2cpu = cpuclk (0:3) * internal pull-up resistor of 120k to vdd on indicated inputs the ICS9250-13 generates all clocks required for high speed risc or cisc microprocessor systems such as intel pentiumpro or cyrix. eight different reference frequency multiplying factors are externally selectable with smooth frequency transitions. spread spectrum may be enabled through i 2 c programming. spread spectrum typically reduces system emi by 8db to 10db. this simplifies emi qualification without resorting to board design iterations or costly shielding. the ICS9250-13 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. recomended application: ? 440lx/ex type chipset motherboard single chip clock solution. ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
2 ICS9250-13 pin descriptions notes: 1: internal pull-up resistor of 240k to 3.3v on indicated inputs 2: bidirectional input/output pins, input logic levels are latched at internal power-on-reset. use 10kohm resistor to program logic hi to vdd or gnd for logic low. r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d 1f e r d d vr w pv 3 . 3 l a n i m o n , y l p p u s r e w o p l a t x , ) 1 : 0 ( f e r 2 0 f e rt u o. k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 3 s f 2 , 1 n it u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f , 5 3 , 9 2 , 8 2 , 2 2 , 6 1 , 9 , 3 3 5 , 7 4 , 1 4 d n gr w pd n u o r g 41 xn i k c a b d e e f d n a ) f p 3 3 ( p a c d a o l l a n r e t n i s a h , t u p n i l a t s y r c 2 x m o r f r o t s i s e r 52 xt u o d a o l l a n r e t n i s a h . z h m 8 1 3 . 4 1 y l l a n i m o n , t u p t u o l a t s y r c ) f p 3 3 ( p a c 4 1 , 6i c p d d vr w pv 3 . 3 l a n i m o n , ) 5 : 0 ( k l c i c p d n a f _ k l c i c p r o f y l p p u s 7 f _ k l c i c pt u ok c o l c i c p g n i n n u r e e r f 1 s f 2 , 1 n it u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f 8 0 k l c i c pt u o. t u p t u o k c o l c i c p 2 s f 2 , 1 n it u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f 3 1 , 2 1 , 1 1 , 0 1) 4 : 1 ( k l c i c pt u o. s t u p t u o k c o l c i c p 5 1 5 k l c i c pt u o) 1 = e d o m , e d o m p o t k s e d n i ( . t u p t u o k c o l c i c p # p o t s _ i c p 1 n i w o l t u p n i n e h w , l e v e l 0 c i g o l t a s k c o l c ) 5 : 0 ( k l c i c p s t l a h ) 0 = e d o m , e d o m e l i b o m n i ( , 6 2 , 1 2 , 0 2 , 8 1 , 7 1 , 7 3 , 6 3 , 1 3 , 0 3 , 7 2 , 5 4 , 3 4 , 2 4 , 0 4 , 9 3 6 4 ) 5 1 : 0 ( m a r d st u o. s t u p t u o k c o l c m a r d s 4 4 , 8 3 , 5 2 , 9 1r d s d d vr w p , s k c o l c z h m 4 2 d n a e r o c l l p , ) 5 1 : 0 ( m a r d s r o f y l p p u s . v 3 . 3 l a n i m o n 3 2a t a d sn ir o f t u p n i a t a di 2 . t u p n i l a i r e s c 4 2k l c sn if o t u p n i k c o l ci 2 t u p n i c 2 38 4 d d vr w pl a n i m o n v 3 . 3 s k c o l c z h m 8 4 r o f y l p p u s 3 3 z h m 4 2t u ok c o l c t u p t u o z h m 4 2 e d o m 2 , 1 n i , e d o m p o t k s e d = 1 , n i p t c e l e s n o i t c n u f 4 5 n i p , 5 1 n i p . t u p n i d e h c t a l . e d o m e l i b o m = 0 4 3 z h m 8 4t u ok c o l c t u p t u o z h m 8 4 0 s f 2 , 1 n it u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f 2 5 , 1 5 , 9 4 , 8 4) 3 : 0 ( k l c u p ct u ow o l = # p o t s _ u p c f i w o l . 2 l d d v y b d e r e w o p , s t u p t u o k c o l c u p c 0 5u p c l d d vr w pl a n i m o n v 3 . 3 r o v 5 . 2 r e h t i e , ) 3 : 0 ( u p c r o f y l p p u s 4 5 1 f e rt u o t u p t u o f e r s i h t ) 1 = e d o m , e d o m p o t k s e d n i ( , k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 . s d a o l s u b a s i r o f r e f f u b r e g n o r t s e h t s i # p o t s _ u p c 1 n i e l i b o m n i ( w o l t u p n i n e h w , l e v e l 0 c i g o l t a s k c o l c ) 3 : 0 ( k l c u p c s t l a h ) 0 = e d o m , e d o m 5 5c i p a o it u oc i p a o i. 1 l d d v y b d e r e w o p z h m 8 1 3 . 4 1 . t u p t u o k c o l c 6 5c i p a o i l d d vr w pl a n i m o n v 3 . 3 r o 5 . 2 r e h t i e , c i p a o i r o f y l p p u s
3 ICS9250-13 functionality v dd 1,2,3 = 3.3v5%, v ddl 1,2 = 2.5v5% or 3.35%, ta=0 to 70c crystal (x1, x2) = 14.31818mhz 5 . 2 _ # 3 . 3 u p c l e v e l t u p n i ) a t a d d e h c t a l ( r o f d e t c e l e s r e f f u b : t a n o i t a r e p o 1d d v v 5 . 2 0d d v v 3 . 3 cpu 3.3#_2.5v buffer selector for cpuclk and ioapic drivers. power management functionality mode pin - power management input control 5 2 n i p , e d o m ) t u p n i d e h c t a l ( 6 4 n i p5 1 n i p 0 # p o t s _ u p c ) t u p n i ( # p o t s _ i c p ) t u p n i ( 1 1 f e r ) t u p t u o ( 5 k l c i c p ) t u p t u o ( # p o t s _ u p c# p o t s _ i c p k l c u p c s t u p t u o k l c i c p ) 5 : 0 ( , f _ k l c i c p , f e r z h m 8 4 / 4 2 m a r d s d n a l a t s y r c c s o o c v 01 w o l d e p p o t sg n i n n u rg n i n n u rg n i n n u rg n i n n u r 11 g n i n n u rg n i n n u rg n i n n u rg n i n n u rg n i n n u r 10 g n i n n u rw o l d e p p o t sg n i n n u rg n i n n u rg n i n n u r 3 s f2 s f1 s f0 s f u p c ) z h m ( m a r d s ) z h m ( k l c i c p ) z h m ( c i p a o i , f e r ) z h m ( 0000 0 0 . 0 90 0 . 0 90 0 . 5 48 1 3 . 4 1 0001 1 0 . 9 81 0 . 9 81 5 . 4 48 1 3 . 4 1 0010 0 0 . 8 80 0 . 8 80 0 . 4 48 1 3 . 4 1 0011 9 9 . 6 89 9 . 6 80 5 . 3 48 1 3 . 4 1 0100 1 9 . 5 81 9 . 5 85 9 . 2 48 1 3 . 4 1 0101 1 0 . 5 81 0 . 5 81 5 . 2 48 1 3 . 4 1 0110 0 0 . 4 80 0 . 4 80 0 . 2 48 1 3 . 4 1 0111 0 0 . 2 80 0 . 2 80 0 . 1 48 1 3 . 4 1 1000 1 0 . 1 81 0 . 1 80 0 . 0 48 1 3 . 4 1 100 1 0 0 . 0 80 0 . 0 85 6 . 1 48 1 3 . 4 1 10 10 1 3 . 3 81 3 . 3 84 2 . 4 38 1 3 . 4 1 10 11 9 4 . 8 69 4 . 8 64 2 . 4 38 1 3 . 4 1 1100 0 0 . 8 70 0 . 8 70 0 . 9 38 1 3 . 4 1 1101 0 0 . 5 70 0 . 5 70 5 . 7 38 1 3 . 4 1 1110 9 9 . 1 79 9 . 1 79 9 . 5 38 1 3 . 4 1 1111 2 8 . 6 62 8 . 6 61 4 . 3 38 1 3 . 4 1
4 ICS9250-13 1. the ics clock generator is a slave/receiver, i 2 c component. it can read back the data stored in the latches for verification. read-back will support intel piix4 "block-read" protocol . 2. the data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode) 3. the input is operating at 3.3v logic levels. 4. the data byte format is 8 bit bytes. 5. to simplify the clock generator i 2 c interface, the protocol is set to use only " block-writes " from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. 6. at power-on, all registers are set to a default condition, as shown. general i 2 c serial interface information the information in this section assumes familiarity with i 2 c programming. for more information, contact ics for an i 2 c programming application note. how to write: ? controller (host) sends a start bit. ? controller (host) sends the write address d2 (h) ? ics clock will acknowledge ? controller (host) sends a dummy command code ? ics clock will acknowledge ? controller (host) sends a dummy byte count ? ics clock will acknowledge ? controller (host) starts sending first byte (byte 0) through byte 5 ? ics clock will acknowledge each byte one at a time . ? controller (host) sends a stop bit how to read: ? controller (host) will send start bit. ? controler (host) sends the read address d3 (h) ? ics clock will acknowledge ? ics clock will send the byte count ? controller (host) acknowledges ? ics clock sends first byte (byte 0) through byte 5 ? controller (host) will need to acknowledge each byte ? controller (host) will send a stop bit notes: controller (host) ics (slave/receiver) start bit address d3 (h) ac k byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack stop bit how to read: controller (host) ics (slave/receiver) start bit address d2 (h) ac k dummy command code ac k dummy byte count ac k byte 0 ac k byte 1 ac k byte 2 ack byte 3 ac k byte 4 ac k byte 5 ac k stop bit how to write:
5 ICS9250-13 byte0: functionality and frequency select register (default = 0) serial configuration command bitmap note 1. default at power-up will be for latched logic inputs to define frequenc,. bits 2, 6:4 are default to 0000. t i bn o i t p i r c s e dd w p 7 t i b n o i t a l u d o m m u r t c e p s d a e r p s % 5 2 . 0 - 0 n o i t a l u d o m m u r t c e p s d a e r p s % 6 . 0 - 1 1 t i b ) 4 : 6 , 2 ( ) 4 : 6 , 2 ( t i b k l c u p c ) z h m ( m a r d s ) z h m ( k l c i c p ) z h m ( x x x 1 e t o n 0 0 0 00 0 . 0 90 0 . 0 90 0 . 5 4 1 0 0 01 0 . 9 81 0 . 9 81 5 . 4 4 0 1 0 00 0 . 8 80 0 . 8 80 0 . 4 4 1 1 0 09 9 . 6 89 9 . 6 80 5 . 3 4 0 0 1 01 9 . 5 81 9 . 5 85 9 . 2 4 1 0 1 01 0 . 5 81 0 . 5 81 5 . 2 4 0 1 1 00 0 . 4 80 0 . 4 80 0 . 2 4 1 1 1 00 0 . 2 80 0 . 2 80 0 . 1 4 0 0 0 11 0 . 1 81 0 . 1 81 5 . 0 4 1 0 0 10 0 . 0 80 0 . 0 80 0 . 0 4 0 1 0 11 3 . 3 81 3 . 3 85 6 . 1 4 1 1 0 19 4 . 8 69 4 . 8 64 2 . 4 3 0 0 1 10 0 . 8 70 0 . 8 70 0 . 9 3 1 0 1 10 0 . 5 70 0 . 5 70 5 . 7 3 0 1 1 19 9 . 1 79 9 . 1 79 9 . 5 3 1 1 1 12 8 . 6 62 8 . 6 61 4 . 3 3 3 t i b , t c e l e s e r a w d r a h y b d e t c e l e s s i y c n e u q e r f - 0 s t u p n i d e h c t a l 4 : 6 , 2 t i b y b d e t c e l e s s i y c n e u q e r f - 1 0 1 t i b n o i t a r e p o l a m r o n - 0 d e l b a n e m u r t c e p s d a e r p s - 1 1 0 t i b g n i n n u r - 0 s t u p t u o l l a e t a t s i r t - 1 0
6 ICS9250-13 byte 1: control register (1 = enable, 0 = disable) notes: 1. inactive means outputs are held low and are disabled from switching. t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) d e v r e s e r ( 6 t i b-1 ) d e v r e s e r ( 5 t i b-x# 2 s f 4 t i b-x# 0 s f 3 t i b8 41 ) t c a n i / t c a ( 3 k l c u p c 2 t i b9 41 ) t c a n i / t c a ( 2 k l c u p c 1 t i b1 51 ) t c a n i / t c a ( 1 k l c u p c 0 t i b2 51 ) t c a n i / t c a ( 0 k l c u p c notes: 1. inactive means outputs are held low and are disabled from switching. byte 2: control register (1 = enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-x# 3 s f 6 t i b71 ) t c a n i / t c a ( f _ k l c i c p 5 t i b5 11 ) t c a n i / t c a ( 5 k l c i c p 4 t i b3 11 ) t c a n i / t c a ( 4 k l c i c p 3 t i b2 11 ) t c a n i / t c a ( 3 k l c i c p 2 t i b1 11 ) t c a n i / t c a ( 2 k l c i c p 1 t i b0 11 ) t c a n i / t c a ( 1 k l c i c p 0 t i b81 ) t c a n i / t c a ( 0 k l c i c p byte 3: control register (1 = enable, 0 = disable) notes: 1. inactive means outputs are held low and are disabled from switching. t i b# n i pd w pn o i t p i r c s e d 7 t i b6 31 ) t c a n i / t c a ( 7 m a r d s 6 t i b7 31 ) t c a n i / t c a ( 6 m a r d s 5 t i b9 31 ) t c a n i / t c a ( 5 m a r d s 4 t i b0 41 ) t c a n i / t c a ( 4 m a r d s 3 t i b2 41 ) t c a n i / t c a ( 3 m a r d s 2 t i b3 41 ) t c a n i / t c a ( 2 m a r d s 1 t i b5 41 ) t c a n i / t c a ( 1 m a r d s 0 t i b6 41 ) t c a n i / t c a ( 0 m a r d s notes: 1. inactive means outputs are held low and are disabled from switching. byte 4: control register (1 = enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b6 21 ) t c a n i / t c a ( 5 1 m a r d s 6 t i b7 21 ) t c a n i / t c a ( 4 1 m a r d s 5 t i b0 31 ) t c a n i / t c a ( 3 1 m a r d s 4 t i b1 31 ) t c a n i / t c a ( 2 1 m a r d s 3 t i b7 11 ) t c a n i / t c a ( 1 1 m a r d s 2 t i b8 11 ) t c a n i / t c a ( 0 1 m a r d s 1 t i b0 21 ) t c a n i / t c a ( 9 m a r d s 0 t i b1 21 ) t c a n i / t c a ( 8 m a r d s byte 5: control register (1 = enable, 0 = disable) notes: 1. inactive means outputs are held low and are disabled from switching. t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) d e v r e s e r ( 6 t i b-1 ) d e v r e s e r ( 5 t i b-1 ) d e v r e s e r ( 4 t i b5 51 ) t c a n i / t c a ( c i p a o i 3 t i b-x# 1 s f 2 t i b-1 ) d e v r e s e r ( 1 t i b4 51 ) t c a n i / t c a ( 1 f e r 0 t i b21 ) t c a n i / t c a ( 0 f e r
7 ICS9250-13 cpu_stop# timing diagram cpu_stop# is an asychronous input to the clock synthesizer. it is used to turn off the cpu clocks for low power operation. cpu_stop# is synchronized by the ICS9250-13 . the minimum that the cpu clock is enabled (cpu_stop# high pulse) is 100 cpu clocks. all other clocks will continue to run while the cpu clocks are disabled. the cpu clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. cpu clock on latency is less than 4 cpu clocks and cpu clock off latency is less than 4 cpu clocks. notes: 1. all timing is referenced to the internal cpu clock. 2. cpu_stop# is an asynchronous input and metastable conditions may exist. this signal is synchronized to the cpu clocks inside the ICS9250-13. 3. all other clocks continue to run undisturbed. (including sdram outputs).
8 ICS9250-13 pci_stop# timing diagram pci_stop# is an asynchronous input to the ICS9250-13 . it is used to turn off the pciclk (0:5) clocks for low power operation. pci_stop# is synchronized by the ICS9250-13 internally. the minimum that the pciclk (0:5) clocks are enabled (pci_stop# high pulse) is at least 10 pciclk (0:5) clocks. pciclk (0:5) clocks are stopped in a low state and started with a full high pul se width guaranteed. pciclk (0:5) clock on latency cycles are only one rising pciclk clock off latency is one pciclk clock. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics9248 device.) 2. pci_stop# is an asynchronous input, and metastable conditions may exist. this signal is required to be synchronized inside the ics9248. 3. all other clocks continue to run undisturbed. 4. cpu_stop# is shown in a high (true) state.
9 ICS9250-13 pins 2, 7, 8, 25, and 26 on the ICS9250-13 serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 4-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm(10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. figs. 1 and 2 show the recommended means of implementing this function. in fig. 1 either one of the resistors is loaded onto the board (selective stuffing) to configure the device?s internal logic. figs. 2a and b provide a single resistor loading option where either solder spot tabs or a physical jumper shared pin operation - input/output pins fig. 1 header may be used. these figures illustrate the optimal pcb physical layout options. these configuration resistors are of such a large ohmic value that they do not effect the low impedance clock signals. the layouts have been optimized to provide as little impedance transition to the clock signal as possible, as it passes through the programming resistor pad(s).
10 ICS9250-13 fig. 2a fig. 2b
11 ICS9250-13 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 70o c; supply voltage v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units operating supply current i dd2.5op c l = 0 pf; select @ 66.8 mhz 20 ma skew 1 t cpu-pci2 v t =1.5 v; vtl=1.25 v 1 2.15 4 ns t cpu-sdram2 vt=1.5 v;vtl=1.25 v 70 500 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v 5% vddl = 2.5v 5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd 0.1 5 a input low current i il1 v in = 0 v; inputs with no pull-up resistors -5 2.0 a input low current i il2 v in = 0 v; inputs with pull-up resistors -200 -100 a operating supply current i dd2.5op c l = 0 pf; select @ 66mhz 160 ma input frequency f i v dd = 3.3 v 12 14.32 16 mhz c in logic inputs 5 pf c inx x1 & x2 pins 27 36 45 pf transition time 1 t tran s to 1st crossing of target freq. 1.3 2 ms settling time 1 t s 0.3 clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. < 2 2 ms t cpu-pci2 v t = 1.5 v 1 2.15 4 ns t cpu-sdram2 v t = 1.5 v 70 500 ps 1 guaranteed by design, not 100% tested in production. input capacitance 1 skew 1
12 ICS9250-13 electrical characteristics - cpuclk t a = 0 - 70o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh2b i oh = -8.0 ma 2 2.4 v output low voltage v ol2b i ol = 12 ma 0.32 0.4 v output high current i oh2b v oh =1.7 v -37 -16 ma output low current i ol2b v ol = 0.7 v 19 26 ma rise time t r2b 1 v ol = 0.4 v, v oh = 2.0 v 1.3 1.9 ns fall time t f2b 1 v oh = 2.0 v, v ol = 0.4 v 1.5 1.9 ns duty cycle d t2b 1 v t = 1.25 v 45 50 55 % skew t sk2b 1 v t = 1.25 v 78 175 ps jitter, cycle-to-cycle tj c y c-c y c2b 1 v t = 1.25 v, normal or spread mode 170 350 ps jitter, one sigma t j 1 s 2b 1 v t = 1.25 v 45 150 ps jitter, absolute t jabs2b 1 v t = 1.25 v -250 120 250 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - sdram t a = 0 - 70o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh3 i oh = -25 ma 2.4 2.85 v output low voltage v ol3 i ol = 20 ma 0.35 0.4 v output high current i oh3 v oh = 2.0 v -60 -40 ma output low current i ol3 v ol = 0.8 v 35 45 ma rise time t r3 1 v ol = 0.4 v, v oh = 2.4 v 1.6 2.4 ns fall time t f3 1 v oh = 2.4 v, v ol = 0.4 v 1.8 2.2 ns duty cycle d t3 1 v t = 1.5 v 46 52 56 % skew 1 t sk1 v t = 1.5 v 325 500 ps 1 guarenteed by design, not 100% tested in production.
13 ICS9250-13 electrical characteristics - pciclk t a = 0 - 70o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh1 i oh = -28 ma 2.4 3 v output low voltage v ol1 i ol = 9.4 ma 0.17 0.4 v output high current i oh1 v oh = 2.0 v -60 -40 ma output low current i ol1 v ol = 0.8 v 41 45 ma rise time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 1.4 2 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 1.4 2 ns duty cycle 1 d t1 v t = 1.5 v 45 50 55 % skew 1 t sk1 v t = 1.5 v 280 500 ps jitter, cycle-to-cycle 1 t j c y c-c y c1a vt = 1.5 v, normal or spread mode 230 400 ps jitter, one sigma 1 t j 1 s 1a v t = 1.5 v 75 150 ps jitter, absolute 1 t jabs1a v t = 1.5 v -250 160 250 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - ioapic t a = 0 - 70o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh4b i oh = -8.0 ma 2 2.3 v output low voltage v ol4b i ol = 12 ma 0.3 0.4 v output high current i oh4b v oh =1.7 v -26 -15 ma output low current i ol4b v ol = 0.7 v 19 27 ma rise time t r4b 1 v ol = 0.4 v, v oh = 2.0 v 1.3 2.2 ns fall time t f4b 1 v oh = 2.0 v, v ol = 0.4 v 1.35 2 ns duty cycle d t4b 1 v t = 1.25 v 45 52 55 % jitter, one sigma t j 1 s 4b 1 v t = 1.25 v 235 350 ps jitter, absolute t jabs4b 1 v t = 1.25 v -800 510 800 ps 1 guaranteed by design, not 100% tested in production.
14 ICS9250-13 electrical characteristics - ref, 24 mhz, 48 mhz t a = 0 - 70o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh5 i oh = -12 ma 2.4 2.9 v output low voltage v ol5 i ol = 10 ma 0.3 0.4 v output high current i oh5 v oh = 2.0 v -30 -20 ma output low current i ol5 v ol = 0.8 v 16 23 ma rise time 1 t r5 v ol = 0.4 v, v oh = 2.4 v 1.95 4 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v 2.1 4 ns duty cycle 1 d t5 v t = 1.5 v 45 51 55 % jitter, one sigma 1 t j 1s5 v t = 1.5 v 170 400 ps jitter, absolute 1 t jabs5 v t = 1.5 v -800 400 800 ps 1 guaranteed by design, not 100% tested in production.
15 ICS9250-13 ssop package l o b m y s s n o i s n e m i d n o m m o c s n o i t a i r a v d n . n i m. m o n. x a m. n i m. m o n. x a m a5 9 0 .1 0 1 .0 1 1 .d a0 2 7 .5 2 7 .0 3 7 .6 5 1 a8 0 0 .2 1 0 .6 1 0 . 2 a8 8 0 .0 9 0 .2 9 0 . b8 0 0 .0 1 0 .5 3 1 0 . c5 0 0 .6 0 0 .5 8 0 0 . ds n o i t a i r a v e e s e2 9 2 .6 9 2 .9 9 2 . ec s b 5 2 0 . 0 h0 0 4 .6 0 4 .0 1 4 . h0 1 0 .3 1 0 .6 1 0 . l4 2 0 .2 3 0 .0 4 0 . ns n o i t a i r a v e e s 0 5 8 x5 8 0 .3 9 0 .0 0 1 . ordering information ics9250 y f-13 pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop revision designator device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx y f - ppp ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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